(1) Field of the Invention
The present invention relates to a CAD (Computer Aided Design) apparatus for aiding design of a printed wiring board, and in particular to placing components to effectively reduce noise, and confirmation of the placement of the components.
(2) Description of the Related Art
In the design of wiring of printed wiring boards, it is imperative to take measures to suppress noise during operation. In particular, electronic circuits that operate with high frequency are prone to generate noise and it is important to take sufficient measures. Conventionally one measure against noise during operation is in the manner of placement of bypass capacitors on the board.
In particular, in printed wiring boards with high frequency signal wires, absorption of high frequency power ripple that happens at the rising edge of a high frequency signal, in other words supply of high frequency current to an IC, is mainly performed by a capacitor. Therefore, in order to reduce electromagnetic noise and improve quality of wiring boards, it is desirable to place the capacitor as close as possible to the IC power pin. This kind of technique is described in “Printed Circuit Board Techniques for EMI Compliance”, Mark I Montrose, IEEE Order No. PC5595 and “HIGH-SPEED DIGITAL DESIGN A Handbook of Black Magic”, Howard W. Johnson and Martin Graham, PTR Prentice-Hall.
Furthermore, conventionally in wiring board placement/wiring CAD, small components such as capacitors, coils (inductors), resistors, filters etc are assigned to large components such as ICs and connectors according to conventional component types or the state of net connection. The components are placed by treating these sets of mutual components as one component, reducing the number of components to be considered on the wiring board overall. This kind of technique is described in “A Method of Suppressing EMI from Printed Circuit Boards by Automatic Placement, Based on Limited Length of Critical Notes”, Shinichi Tanimoto et. al, Shingaku Giho, EMCJ99-92, pp. 17–22, 1999.
However, when components are assigned based on component type, there is no differentiation between capacitors with high capacity for supplying low frequency current such as electrolytic capacitors and tantalum capacitors, and low capacity ceramic capacitors for supplying high frequency current in relation to main, large components (ICs), but rather all are simply treated as capacitors. For this reason, as with capacitors C6 to C8 (that have a lower capacity than C1 to C3) in FIG. 1, the capacitors are assigned in clusters. Therefore the component assigning is not carried out appropriately, requiring the user to make revisions. Moreover, capacitors that supply higher frequency current should be placed closer to the IC power pin. However, it has become common recently for ICs to have a plurality of power pins, and also many pin pair combinations of IC power pins and power pins of pluralities of capacitors, making selecting and wiring suitable pin pairs difficult.
A CAD apparatus for confirming whether the placement of a bypass capacitor is appropriate is disclosed in Japanese laid-open patent application H10-07560 (Computer Aided Design System).
This CAD apparatus makes confirmation of the placement of bypass capacitors possible by displaying on the board the effective range for eliminating noise for each bypass capacitor.
FIG. 2 shows a display example of a wiring board being designed displayed on the monitor of the CAD apparatus disclosed in Japanese laid-open patent application H10-07560.
At this point, a bypass capacitor 2110, an IC 2120, and an IC 2130 have been placed on a wiring board 2101 shown in FIG. 2.
The effective range for eliminating noise with the bypass capacitor 2110 is shown by an ellipse 2141 and an ellipse 2142. Here, the ellipse 2141 shows the range in which noise elimination by the bypass capacitor 2110 is highly effective, while ellipse 2124 shows the range in which noise elimination by the bypass capacitor 2110 is moderately effective.
Designers, referring to these effective ranges for eliminating noise, can confirm the placement of bypass capacitors by judging whether each pin of the components placed on a wiring board is in an effective range for eliminating noise by a bypass capacitor.
Here, the 4 pins on the left side of the IC 2120 are within the ellipse 2141, therefore noise elimination is estimated to be highly effective. The 4 pins on the right side of the IC 2120 are within the ellipse 2142, therefore noise elimination is estimated to be moderately effective. None of the pins of IC 2130 is within either the ellipse 2141 or the ellipse 2142, therefore noise elimination is estimated to be less than moderately effective.
However, in a display such as the above, as the number of bypass capacitors placed on a wiring board increases, the number of ellipses also increases. As a result, the ellipses overlap and the display becomes extremely difficult to see when the number of bypass condensers exceeds a certain level.
Furthermore, because each pin of a component has different operating characteristics, such as operation frequency, there are cases in which each pin conforms to a different bypass capacitor. In such cases, in a display such as the above-described, it is difficult to know which bypass capacitor is effective with which pin of which component, possibly resulting in errors in judgement.
In addition, capacitors have capacities, so even if the characteristics match, if the capacity is insufficient the noise elimination effect will be inadequate. However, in a display such as above, the capacity of bypass capacitors is not considered so it is difficult to detect if the capacity is insufficient.
Moreover, a judgement method using a display such as the above-described is inaccurate because the effectiveness of a bypass capacitor is judged by the linear distance on the surface between the bypass capacitor and a pin on the board. The reason for this inaccuracy is that the effectiveness of a bypass capacitor is not determined by the linear distance on a surface, but rather depends on the length of the path determined by the wiring pattern along which the harmonic content of the transient current flows.